A Simulator for a Multithreaded Processor

This paper presents a simulator of a multithread processor, which is developed, with a minimum architectural impact, on a conventional RISC platform. The multithread processor supports a mixture of controland data-flow model of execution with hardware primitives for scheduling and synchronization. The simulator permits, by changing the processor parameters such as the cache size, the number of contexts and the number of resources, to design, debug, test and evaluate the performance of multithreaded programs with a minimum efforts. The results achieved indicate that the multithread simulator exhibits high performance by switching between ready contexts and hence overlapping the computation with memory accesses to reduce the processor idle time.